Intro - zero to hero verilog

This is a zero to hero tracking of my journey in fpga programming using verilog. This will be mostly a list of projects that I came up with that would increase in difficulty and general knowledge.

Some things to consider:

• I will mostly be using tools from the Intel FPGA suite which are free, namely quartus, and possibly questa.
• I am using a chinese board bought from aliexpress that has a cyclone 10 LP fpga chip. latest link
• Documentation on the board I am using can be found on AIDeveloperMonster repo which also has a nice LED demo.
• All code shall be made available at some point on verilog journey
• There won't be a lot of details on how I did things, figure things out they shouldn't be that hard.
• Most of the projects have a template at base as to not interact much with the Quartus app, it should be possible to do most of the things through the cli alone. You can find the template here
• Some things may be undefined which means only the idea exists but nothing was done yet.
• I will be using verilog as for the programming language.

Verilog is nothing to be scared of, tldr for it - everything is based on modules which get registered and run continuously, everything runs in parallel just as a fancy for loop.

Now for the projects:

1. Turn on the LEDs
2. GCD
3. UART
4. Mouse Microphone
5. Crypto stuff
6. Other comms
7. Work distribution
8. My progress so far

Turn on the LEDs

The classic hello world project for any hardware enthusiast. Find out how to define the LEDs, define some inputs, clocks and resets. If it is too easy, try doing a debouncer for a button and do a counter.

GCD

Just give two numbers as constants, compute the gratest common divisor and display the output on the LEDs. Play around setting PLLs (faster/slower clocks), try to max out the speed of your board with one clock and have a slower than usual one update the LEDs.

UART

UART is at the base of data communication, get single byte on Rx from the computer and send it back on Tx or display it on the LEDs. Try sending numbers for the previous GCD project.

Find out max speeds, try working around limitations. UART is usually done over the wire but nothing stopping you from doing it through fiber between multiple boards.

Microphone with mouse sensor (undefined)

Get a mouse optic sensor, write a driver to read data, send the data over to the PC.

Crypto stuff (undefined)

• factorization of a large number: Pollards rho, p+1, or p-1.
• prime number generator
• random number generator: possibly quantum rng with a laser diode, a 50/50 pbs and some photoresistors, guide here
• bitcoin solo miner

Make them, make them faster, parallelise as much as possible.

Other comms (undefined)

Work with other communication protocols:

• 10base-t1l - industrial internet protocol over 3 wires
• rj45 - cost effective high speed (internet stack)
• sfp - the fancy internet ports that support both rj45 and fiber optic

Some of them might require extra chips like possible SERDES ICs or might be possible through your board. Might need to design a breakout board or just a random PCB just to be able to connect stuff together.

Work distribution (undefined)

Use multiple boards, tie them together with whatever protocol, have them work on the same stuff to get a result faster.

My progress so far

The template

The template that helps one start a quartus project also holds the following:

• leds interface
• uart communication: send byte or number
• math: gcd, comba worded multiplication to make use of the dsp, addition that hopes of reducing the area

The template

Pollards rho

The pollard's rho implementation is based on a worded comba multiplication in order to reduce the area on chip. Doing a large multiplication, and doing it fast, and with a low area is quite the challenge. The basic POC factoring 323 which is 17*19 can be found in the pollards rho master branch. The implementation of factoring the RSA 896 (check the rsa challenge) feels pretty much impossible on a Cyclone 10 LP and might be moved to a Cyclone 5, implementation can be seen on the pollards rho rsa 896 branch.

The multiplications are done in the Montgomery domain as to avoid doing divisions.

Well ... I kinda gave up on the project after realizing that its impossible to fit properly on the board ... or is it? I stumbled upon the maping file and I something called "Memory Blocks" and I was "Ok ... do I get that expensive thing that people call RAM?". It took sometime, but now everything for the rsa896 fits nicely on a Cyclone10 LP chip -- that means that we've gone from about 120k LUTs to 80k compiling for the Cyclone V from a DE10-Nano then now we are on about 4k LUTs fitting on a really budget friendly and low power board. You can see the implementation using ram on the rsa896 ram branch